1. Field of the Invention
This invention relates generally to digital logic circuits and more specifically to synchronization between digital logic circuits operating at different clock rates.
2. Discussion of Related Art
Most modern digital systems use clocks to control the time of operation of the various circuit components within the system. In designing the digital system, care is taken to ensure that whenever one circuit element is clocked to perform an operation, the inputs to that circuit element required to complete that operation have already been generated. In this way, all of the circuit elements can operate together to produce the expected result.
Some complex systems include multiple clocks. Each clock might control the timing of operations within some subset of the circuit elements in the overall system. These subsets of elements are often called “clock domains.” Multiple clock domains might be used, for example, where some portions of the system perform high frequency measurements or high speed signal processing. These portions of the system might require a relatively high frequency clock. Other portions of the system might perform relatively low frequency control functions and therefore be implemented with less expensive logic clocked with a lower frequency clock.
Automatic test equipment of the type used to test semiconductor devices during their manufacture is one example of a type of system having multiple clock domains. FIG. 1 shows in block diagram form a piece of automatic test equipment, referred to generally as a “tester.” Tester 20 includes a computer workstation 22, which serves as an operator interface and provides overall control to tester 20.
Tester 20 includes a test head 24 that contains many electronic circuit cards that contain circuitry to perform the many functions required for a tester 20 to generate and measure all of the signals necessary to test a semiconductor device under test (DUT) 90.
Tester 20 is shown to contain multiple instrument cards 30. The instrument cards contain circuitry to generate or measure signals as needed during a test of a semiconductor device. Instrument card 30A is an example of a digital instrument card that generates and measures digital signals as part of a test. Card 30A includes a clock module 40 that generates a clock that times circuitry on instrument card 30A. Clock module 40 might be a clock module such as is described in U.S. Pat. No. 6,188,253 to Gage et al., entitled ANALOG CLOCK MODULE, which is hereby incorporated by reference in its entirety.
In the example of FIG. 1, clock module 40 contains a direct digital synthesis (DDS) circuit 42 and a phase lock loop and filter circuit 44. The phase lock loop and filter circuit 44 outputs a clock signal that has a programmable frequency. The frequency of the clock produced by clock module 40 is preferably programmed to execute test functions at a rate appropriate for a specific device under test. Each of the other instruments 30 might similarly contain a clock module 40, with each being programmed to generate a clock at a frequency appropriate for the test functions to be performed by that instrument.
The digital instrument card 30A also includes formatting and PIN electronics 48, which generate and measure digital signals applied to a device under test (DUT) 90. The value of those signals and the precise time at which they are applied to DUT 90 is controlled by programming of pattern generation and timing circuitry 46.
Tester 20 might include multiple digital instruments so that many digital signals can be generated and measured simultaneously. Others of the instruments 30 will perform different functions. Many semiconductor devices generate or operate on analog signals. For example, the semiconductor chips used in disk drive controllers, cellular telephones and audio-video systems all generate or operate on signals in analog form in addition to signals that are in digital form. To test these chips, some of the instruments 30 will generate or measure analog signals.
To fully test DUT 90, it is usually necessary to ascertain that DUT 90 generates a specific analog signal in response to a specific digital input or that DUT 90 generates a specific digital output in response to a certain analog input signal. Often, it is not sufficient to know only that DUT 90 generated an analog or digital signal with the expected value. It is often necessary to also know that the signal was generated at the appropriate time relative to the input. Therefore, it is often necessary that the various instruments 30 within tester 20 be synchronized with each other.
In this context, “synchronized” means that the instruments produce some signals with a predictable time relationship. Often, in a test system, it is not necessary that events in different instruments occur simultaneously and “synchronized” events need not be “simultaneous.” Rather, it is often more important in a test system that certain events occur with the same relative time whenever a test is performed. If the test system does not generate signals with the same relative timing on each test, differences in the test results might be attributable to differences in the way test signals were generated or measured rather than actual differences in the device under test. On the other hand, if events have a predictable time relationship, differences from test to test can be more readily associated with defects in the device under test, resulting in a more accurate tester. Additionally, if two events have a predictable time relationship that can be measured, the tester can often be calibrated such that the events occur with a controlled time relationship. However, “synchronous” does not necessarily imply that the relative time of two events is controlled to have a specific value.
FIG. 1 shows that tester 20 includes various region cards 28. Each region card 28 is connected to multiple instrument cards 30. The region card provides a reference clock signal and a synchronization signal to the various instruments 30 connected to that region card. All of the region cards 28 receive a reference clock from a reference clock generator 34 which is located on a master region card 26. This reference clock is fanned out to each of the instrument cards 30 in a region through reference clock fan out circuit 38 on each of the region cards 28. Likewise, a synchronization signal generated in master region card 26 is distributed to each of the region cards 28 and fanned out in synchronization signal fan out circuitry 36 to the instrument cards 30 within that region.
Various other synchronization schemes might be used within a tester. For example, connections might be provided from instrument to instrument through which specific instruments might be synchronized. Generally, though, when multiple instruments have access to a synchronization signal, they can all set a time reference and operate to control events relative to that time reference.
We have recognized that it is particularly challenging to synchronize low frequency digital circuitry with high frequency digital circuitry. As with tester 20 in FIG. 1, the reference clock generally needs to be a low frequency clock because a high frequency clock can not maintain its accuracy as it is routed through a tester. High frequency clocks are generated, such as in a clock generation module 40.
FIG. 2 is a generic block diagram that represents a scenario in which digital circuitry 210 in a low frequency clock domain needs to be synchronized with digital circuitry 212 in a high frequency clock domain. FIG. 2 shows in general the low frequency clock denoted LF_CLK and the high frequency clock HF_CLK. A synchronization signal, denoted SYNC is generated in low frequency digital circuitry 210. FIG. 2 shows the low frequency clock and high frequency clock signals in idealized form. Each period of the clock is shown to be perfectly uniform and the periods are perfectly spaced. However, all clock signals have some amount of jitter.
FIG. 3 illustrates a difficulty that can occur when a synchronization signal, SYNC, that is intended to synchronize high frequency digital circuitry 212 with low frequency digital circuitry 210 is aligned with the low frequency clock, LF_CLK. SYNC pulse 310 has nominal edges 312 and 314. However, LF_CLK has jitter, meaning that the actual position of the leading and trailing edges of SYNC pulse 310 might occur earlier or later than the nominal positions. The leading edge of the SYNC pulse 310 might occur between 312A and 312B. The trailing edge of SYNC pulse 310 might occur between times 314A and 314B. The differences between time 312A and 312B in between times 314A and 314B represents the jitter, J, in LF_CLK.
If SYNC pulse 310 is used to synchronize high frequency digital circuitry 212, the variation in the leading edge 312 or falling edge 314 of the SYNC pulse translates into variability of the timing of the output signal from high frequency digital circuitry 212.
Signal 320A represents an output of high frequency digital circuitry 212 that is synchronized to SYNC pulse 310 that might occur in one run of a test program. Signal 320A depicts an output of circuitry clocked by HF_CLK performing some function in the interval between the leading and trailing edge of SYNC pulse 310. For example, a high frequency signal might be transmitted during this interval.
HF_CLK is a higher frequency signal than LF_CLK used for timing SYNC pulse 310. It therefore has multiple periods in the interval spanned by SYNC pulse 310. Signal 320A is shown to have multiple signal transitions corresponding to the periods of HF_CLK. One of these signal transitions is shown at 322A to be aligned with the nominal rising edge 312 of SYNC pulse 310. If the rising edge of SYNC pulse 310 occurs at the nominal time as indicated by edge 312, the output signal of high frequency digital circuit 212 will have the timing as indicated at 322A. However, if jitter on signal 310 causes the leading edge of SYNC pulse 310 to occur at 312A, the output of high frequency digital logic 212 will appear as shown as signal 320B. In signal 320B signal transition 322B aligns with leading edge 312A.
A similar difference in timing can occur when the high frequency digital logic 212 is synchronized with the falling edge of SYNC pulse 310. The falling edge might occur at any time in the interval bounded by 314A and 314B. Signal 320A shows the output when the falling edge of SYNC pulse 310 occurs at 314A. In contrast, signal 320B denotes the output when the falling edge of SYNC pulse 310 occurs as late as 314B.
Pulses in high frequency digital circuit 212 synchronized to the leading and falling edges of SYNC pulse 310 will occur at some time during the intervals denoted E. Because jitter is random, the precise time within that interval cannot be known from cycle to cycle. Further, because the jitter need not be the same on both the rising and falling edges of SYNC pulse 310, the relative timing of events within high frequency digital logic circuit 212 might be impacted by the jitter. Consequently, there might be a difference from test to test in the timing of an event in the output of high frequency digital logic 212. In the example where a signal is generated in the interval between the leading and trailing edges of SYNC pulse 310, that signal might be generated for an interval IA as shown in signal 320A or interval IB as shown in signal 320B. Which interval will occur in any specific test will depend on the jitter on LF_CLK, which is generally unpredictable.
Such differences in timing can lead to undesirable results in the operation of high frequency digital logic 212. Uncertainty in the relative timing of events might cause unpredictable test results, or even errors in operation of high frequency logic 212.